View LSM303D_7924949.PDF datasheet online --- IC-ON-LINE

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this is information on a product in full production. november 2013 docid023312 rev 2 1/52 LSM303D ultra-compact high-performance ecompass module: 3d accelerometer and 3d magnetometer datasheet - production data features ? 3 magnetic field channels and 3 acceleration channels ? 2/4/8/12 gauss magnetic full scale ? 2/4/6/8/16 g linear acceleration full scale ? 16-bit data output ? spi / i 2 c serial interfaces ? analog supply voltage 2.16 v to 3.6 v ? power-down mode / low-power mode ? programmable interrupt generators for free- fall, motion detection and magnetic field detection ? embedded temperature sensor ? embedded fifo ? ecopack ? , rohs and ?green? compliant applications ? tilt-compensated compasses ? map rotation ? position detection ? motion-activated functions ? free-fall detection ? click/double-click recognition ? pedometers ? intelligent power saving for handheld devices ? display orientation ? gaming and virtual reality input devices ? impact recognition and logging ? vibration monitoring and compensation description the LSM303D is a system-in-package featuring a 3d digital linear acceleration sensor and a 3d digital magnetic sensor. the LSM303D has linear acceleration full scales of 2 g / 4 g / 6 g / 8 g / 16 g and a magnetic field full scale of 2 / 4 / 8 / 12 gauss . the LSM303D includes an i 2 c serial bus interface that supports standard and fast mode (100 khz and 400 khz) and spi serial standard interface. the system can be configured to generate an interrupt signal for free-fall, motion detection and magnetic field detection. thresholds and timing of interrupt generators are programmable by the end user. magnetic and accelerometer blocks can be enabled or put into power-down mode separately. the LSM303D is available in a plastic land grid array package (lga) and is guaranteed to operate over an extended temperature range from -40 c to +85 c. lga-16 (3x3x1 mm) table 1. device summary part number temperature range [c] package packaging LSM303D -40 to +85 lga-16 tray LSM303Dtr -40 to +85 lga-16 tape and reel www.st.com
contents LSM303D 2/52 docid023312 rev 2 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.2 sensor i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 set/reset pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 linear acceleration sensor sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 magnetic sensor sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 zero-gauss level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 digital interface power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
docid023312 rev 2 3/52 LSM303D contents 52 5.5 high-current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 temp_out_l (05h), temp_out_h (06h) . . . . . . . . . . . . . . . . . . . . . . . 30 8.2 status_m (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 out_x_l_m (08h), out_x_h_m (09h) . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.4 out_y_l_m (0ah), out_y_h_m (0bh) . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.5 out_z_l_m (0ch), out_z_h_m (0dh) . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.7 int_ctrl_m (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.8 int_src_m (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.9 int_ths_l_m (14h), int_ths_h_m (15h) . . . . . . . . . . . . . . . . . . . . . . 32 8.10 offset_x_l_m (16h), offset_x_h_m (17h) . . . . . . . . . . . . . . . . . . . 33 8.11 offset_y_l_m (18h), offset_y_h_m (19h) . . . . . . . . . . . . . . . . . . . 33 8.12 offset_z_l_m (1ah), offset_z_h_m (1bh) . . . . . . . . . . . . . . . . . . 33 8.13 reference_x (1ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.14 reference_y (1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.15 reference_z (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.16 ctrl0 (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17 ctrl1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.18 ctrl2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.19 ctrl3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.20 ctrl4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.21 ctrl5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
contents LSM303D 4/52 docid023312 rev 2 8.22 ctrl6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.23 ctrl7 (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.24 status_a (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.25 out_x_l_a (28h), out_x_h_a (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.26 out_y_l_a (2ah), out_y_h_a (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.27 out_z_l_a (2ch), out_z_h_a (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.28 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.29 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.30 ig_cfg1 (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.31 ig_src1 (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.32 ig_ths1 (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.33 ig_dur1 (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.34 ig_cfg2 (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.35 ig_src2 (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.36 ig_ths2 (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.37 ig_dur2 (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.38 click_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.39 click_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.40 click_ths (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.41 time_limit (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.42 time_latency (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.43 time window (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.44 act_ths (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.45 act_dur (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid023312 rev 2 5/52 LSM303D list of tables 52 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 11. sad+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 14. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 23 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 23 table 16. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 17. status_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. status_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 19. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. int_ctrl_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 21. int_ctrl_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 22. int_src_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23. int_src_m register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 24. int_ths_l_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 25. int_ths_h_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 26. offset_x_l_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 27. offset_x_h_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 28. offset_y_l_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 29. offset_y_h_m register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 30. offset_z_l_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 31. offset_z_h_m register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 32. ctrl0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 33. ctrl0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 34. ctrl1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 35. ctrl1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 36. acceleration data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 37. ctrl2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 38. ctrl2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 39. acceleration anti-alias filter bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 40. acceleration full-scale selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 41. ctrl3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 42. ctrl3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 43. ctrl4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 44. ctrl4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 45. ctrl5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 46. ctrl5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 47. magnetic data rate configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 48. ctrl6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of tables LSM303D 6/52 docid023312 rev 2 table 49. ctrl6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 50. magnetic full-scale selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 51. ctrl7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 52. ctrl7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 53. high-pass filter mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 54. magnetic sensor mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 55. status_a register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 56. status_a register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 57. fifo_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 58. fifo_ctrl register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 59. fifo mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 60. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 61. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 62. ig_cfg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 63. ig_cfg1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 64. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 65. ig_src1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 66. ig_src1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 67. ig_ths1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 68. ig_ths1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 69. ig1_dur1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 70. ig1_dur1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 71. ig_cfg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 72. ig_cfg2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 73. interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 74. ig_src2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 75. ig_src2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 76. ig2_ths2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 77. ig2_ths2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 78. ig_dur2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 79. ig_dur2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 80. click_cfg register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 81. click_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 82. click_src register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 83. click_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 84. click_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 85. click_ths register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 86. time_limit register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 87. time_limit register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 88. time_latency register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 89. time_latency register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 90. time_window register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 91. time_window register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 92. act_ths register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 93. act_ths register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 94. act_dur register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 95. act_dur register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 96. lga 3x3x1.0 16l mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 97. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
docid023312 rev 2 7/52 LSM303D list of figures 52 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4. i 2 c slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. LSM303D electrical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 10. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. lga 3x3x1.0 16l mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
block diagram and pin description LSM303D 8/52 docid023312 rev 2 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 pin description figure 2. pin connections y+ z+ y- z- x+ x- mux cs scl/spc i (a) + - charge amplifier sensing block sensing interface a/d control logic converter di spi / i2c sda/sdi/sdo sdo/sa0 mux i (m) + - charge amplifier y+ z+ y- z- x+ x- interrupt gen. clock trimming circuits reference offset circuits built-in circuits set/reset temperature fifo sensor int1 int2 am12676v1 direction of detectable magnetic fields direction of detectable accelerations top view 1 5 9 13 (bottom view) y 1 x z pin 1 indicator x z y top view am12677v1
docid023312 rev 2 9/52 LSM303D block diagram and pin description 52 table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 setc s/r capacitor connection (c 2 ) 3 setp s/r capacitor connection (c 2 ) 4 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 5 gnd 0 v supply 6 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 7 sdo sa0 spi serial data output (sdo) i 2 c less significant bit of the device address (sa0) 8cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 9 int 2 interrupt 2 10 reserved connect to gnd 11 int 1 interrupt 1 12 gnd 0 v supply 13 gnd 0 v supply 14 vdd power supply 15 c1 capacitor connection (c 1 ) 16 gnd 0 v supply
module specifications LSM303D 10/52 docid023312 rev 2 2 module specifications 2.1 sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 2.5 v. the operational power supply range is from 2.16 v to 3.6 v. table 3. sensor characteristics symbol parameter test conditions min. typ. (1) max. unit la_fs linear acceleration measurement range (2) 2 g 4 6 8 16 m_fs magnetic measurement range 2 gauss 4 8 12 la_so linear acceleration sensitivity linear acceleration fs = 2 g 0.061 m g /lsb linear acceleration fs = 4 g 0.122 linear acceleration fs = 6 g 0.183 linear acceleration fs = 8 g 0.244 linear acceleration fs = 16 g 0.732 m_so magnetic sensitivity magnetic fs = 2 gauss 0.080 mgauss/ lsb magnetic fs = 4 gauss 0.160 magnetic fs = 8 gauss 0.320 magnetic fs = 12 gauss 0.479 la_tcso linear acceleration sensitivity change vs. temperature 0.01 %/c m_tcso magnetic sensitivity change vs. temperature 0.05 %/c la_tyoff linear acceleration typical zero- g level offset accuracy (3),(4) 60 m g la_tcoff linear acceleration zero- g level change vs. temperature max delta from 25 c 0.5 m g /c la_an linear acceleration noise density linear acceleration fs = 2 g ; odr = 100 hz 150 m_r magnetic noise density magnetic fs = 2 gauss; lr setting ctrl5 (m_res [1,0]) = 00b 5 mgauss/ rms ug hz ?? ?
docid023312 rev 2 11/52 LSM303D module specifications 52 2.2 temperature sensor characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (b) . m_cas magnetic cross-axis sensitivity cross field = 0.5 gauss applied = 3 gauss 1 %fs/ gauss m_ef maximum exposed field no permanent effect on sensor performance 10000 gauss m_df magnetic disturbance field sensitivity starts to degrade. automatic s/r pulse restores the sensitivity (5) 20 gauss la_st linear acceleration self-test positive difference (6) 2 g range, x-, y-axis ast = 1 see table 37 70 1700 m g 2 g range, z-axis ast = 1 see table 37 70 1700 top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. verified by wafer level test and measurement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. offset can be eliminated by enabling the built-in high-pass filter. 5. set/reset pulse is automatically applied at each conversion cycle. 6. ?self-test output change? is defined as: output[mg] (ctrl2 ast bit =1) - output[mg] ( ctrl2 ast bit =0 ) . table 3. sensor characteristics (continued) symbol parameter test conditions min. typ. (1) max. unit b. the product is factory calibrated at 2.5 v. table 4. temperature sensor characteristics symbol parameter test conditions min. typ. (1) max. unit tsdr temperature sensor output change vs. temperature - 8 lsb/c todr temperature refresh rate m_odr [2:0] (2) hz top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. refer to table 47: magnetic data rate configuration .
module specifications LSM303D 12/52 docid023312 rev 2 2.3 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted. table 5. electrical characteristics symbol parameter test conditions min. typ. (1) max. unit vdd supply voltage 2.16 3.6 v vdd_io module power supply for i/o 1.71 1.8 vdd+0.1 idd ecompass (2) current consumption in normal mode (3) lr setting ctrl5 (m_res [1,0]) = 00b, see table 45 300 a iddsl current consumption in power-down mode (4) 1 a top operating temperature range -40 +85 c 1. typical specifications are not guaranteed. 2. ecompass : accelerometer and magnetic sensor. 3. magnetic sensor setting odr = 6.25 hz, accelerometer sensor odr = 50 hz and magnetic high-resolution setting. 4. linear accelerometer and magnetic sensor in power-down mode.
docid023312 rev 2 13/52 LSM303D module specifications 52 2.4 communication interface characteristics 2.4.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io for both input and output ports. table 6. spi slave timing values symbol parameter value (1) unit min. max. t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 5 ns t h(cs) cs hold time 20 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 5 t dis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
module specifications LSM303D 14/52 docid023312 rev 2 2.4.2 sensor i 2 c - inter-ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io for both ports. table 7. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. c b = total capacitance of one bus line, in pf. sd a scl t f ( sd a ) t su ( sp) t w( scll) t su ( sd a ) t r( sd a ) t su ( sr) t h( st) t w( sclh ) t h( sd a ) t r( scl) t f ( sc l) t w( sp: sr) start repeated sta rt sto p sta rt
docid023312 rev 2 15/52 LSM303D module specifications 52 2.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 8. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (scl/spc, sda/sdi/sdo, sdo/sa0, cs) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3,000 for 0.5 ms g 10,000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3,000 for 0.5 ms g 10,000 for 0.1 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part.
terminology LSM303D 16/52 docid023312 rev 2 3 terminology 3.1 set/reset pulse the set/reset pulse is an automatic operation performed before each magnetic acquisition cycle to recover the initial magnetization state of the sensor and therefore the linearity of the sensor itself. 3.2 sensitivity 3.2.1 linear acceleration sensor sensitivity sensitivity describes the gain of the sensor and can be determined, for example, by applying 1 g acceleration to it. as the sensor can measure dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 3.2.2 magnetic sensor sensitivity sensitivity describes the gain of the sensor and can be determined, for example, by applying a magnetic field of 1 gauss to it. 3.3 zero- g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady-state on a horizontal surface measures 0 g on the x-axis and 0 g on the y-axis, whereas the z-axis measures 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as two?s complement). a deviation from the ideal value in this case is called zero- g offset. offset is, to some extent, a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. 3.4 zero- gauss level zero- g auss level offset describes the deviation of an actual output signal from the ideal output if no magnetic field is present. thanks to the set/reset pulse and to the magnetic sensor read-out chain, the offset is dynamically cancelled. the zero- g auss level does not show any dependencies on temperature and power supply.
docid023312 rev 2 17/52 LSM303D functionality 52 4 functionality 4.1 self-test the self-test allows checking the linear acceleration sensor functionality without moving the sensor. the self-test function is off when the self-test bit (ast) is programmed to ?0?. when the self-test bit is programmed to ?1?, an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs exhibit a change in their dc levels which are related to the selected full scale through the device sensitivity. when the self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified inside section 2.1 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 4.2 temperature sensor the LSM303D features an internal temperature sensor. temperature data can be enabled by setting the temp_en bit on the ctrl5 (24h) register to 1. both the temp_out_h and temp_out_l registers must be read. temperature data is stored inside temp_out_l (05h), temp_out_h (06h) as two?s complement data in 12-bit format, right-justified. the output data rate of the temperature sensor is set by m_odr [2:0] in ctrl5 (24h) and is equal to the magnetic sensor output data rate. 4.3 fifo the LSM303D embeds an acceleration data fifo for each of the three output channels, x, y and z. this allows consistent power saving for the system, as the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work according to four different modes: bypass mode, fifo mode, stream mode and stream-to-fifo mode. each mode is selected by the fifo_mode bits. programmable threshold level, fifo_empty or fifo_full events can be enabled to generate dedicated interrupts on the int 1 or int 2 pin. bypass mode in bypass mode, the fifo is not operational and for this reason it remains empty. as described in figure 5 , for each channel only the first address is used. the remaining fifo slots are empty. fifo mode in fifo mode, data from x, y and z channels are stored in the fifo. a fifo threshold interrupt can be enabled in order to be raised when the fifo is filled to the level specified by the internal register. the fifo continues filling until it is full. when full, the fifo stops collecting data from the input channels.
functionality LSM303D 18/52 docid023312 rev 2 stream mode in stream mode, data from x, y and z measurements are stored in the fifo. a fifo threshold interrupt can be enabled and set as in fifo mode.the fifo continues filling until it?s full. when full, the fifo discards the older data as the new arrive. stream-to-fifo mode in stream-to-fifo mode, data from x, y and z measurements are stored in the fifo. a fifo threshold interrupt can be enabled in order to be raised when the fifo is filled to the level specified by the internal register. the fifo continues filling until it?s full. when full, the fifo discards the older data as the new arrive. once a trigger event occurs, the fifo starts operating in fifo mode. bypass-to-stream mode in bypass-to-stream mode, the fifo starts operating in bypass mode and once a trigger event occurs (related to ig_cfg1 (30h) register events), the fifo starts operating in stream mode. retrieving data from fifo fifo data is read from the out_x_a, out_y_a and out_z_a registers. when the fifo is in stream, stream-to-fifo, bypass-to-stream or fifo mode, a read operation to the out_x_a, out_y_a or out_z_a registers provides the data stored in the fifo. each time data is read from the fifo, the oldest x, y and z data are placed in the out_x_a, out_y_a and out_z_a registers and both single read and read_burst operations can be used. 4.4 factory calibration the ic interface is factory calibrated. the trim values are stored inside the device in nonvolatile memory. anytime the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. this allows the user to use the device without further calibration.
docid023312 rev 2 19/52 LSM303D application hints 52 5 application hints figure 5. LSM303D electrical connections 5.1 external capacitors the c 1 and c 2 external capacitors should be low sr value ceramic type construction (typ. recommended value 200 m ? ). reservoir capacitor c 1 is nominally 4.7 f in capacitance, with the set/reset capacitor c 2 nominally 0.22 f in capacitance. the device core is supplied through the vdd line. power supply decoupling capacitors (c 4 = 100 nf ceramic, c 3 = 10 f al) should be placed as near as possible to the supply pin of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). the functionality of the device and the measured acceleration/magnetic field data is selectable and accessible through the i 2 c/spi interfaces. the functions, the threshold and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user through the i 2 c/spi interfaces. 5.2 pull-up resistors if an i 2 c interface is used, pull-up resistors (recommended value 10 k ? ) must be placed on the two i 2 c bus lines. cs c 3 = 10f vdd c 4 = 100nf gnd vdd_io sdo/sa0 sda/sdi/sdo int 1 scl/spc digital signal from/to signal controller. signal levels are defined by proper selection of vdd_io 1 5 8 13 top view 6 9 14 16 9 5 int 2 c 1 = 4.7f c 2 =0.22f am12678v1
application hints LSM303D 20/52 docid023312 rev 2 5.3 digital interface power supply this digital interface, dedicated to the linear acceleration and to the magnetic field signal, is capable of operating with a standard power supply (vdd) or using a dedicated power supply (vdd_io). 5.4 soldering information the lga package is compliant with ecopack ? , rohs and ?green? standards. it is qualified for soldering heat resistance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www .st.com/mems . 5.5 high-current wiring effects high current in wiring and printed circuit traces can be the cause of errors in magnetic field measurements for compassing. conductor-generated magnetic fields add to the earth?s magnetic field creating errors in compass heading computations. keep currents higher than 10 ma a few millimeters further away from the sensor ic.
docid023312 rev 2 21/52 LSM303D digital interfaces 52 6 digital interfaces the registers embedded in the LSM303D may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw-configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e connected to vdd_io). 6.1 i 2 c serial interface the LSM303D i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bi-directional line used for sending and receiving the data to/from the interface. both lines must be connected to vdd_io through external pull-up resistors. when the bus is free, both lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with normal mode. table 9. serial interface pin description pin name pin description cs i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl/spc i 2 c serial clock (scl) spi serial port clock (spc) sda/sdi/sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo/sa0 spi serial data output (sdo) i 2 c less significant bit of the device address (sa0) table 10. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces LSM303D 22/52 docid023312 rev 2 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LSM303D is 00111xxb, whereas the xx bits are modified by the sdo/sa0 pin in order to modify the device address. if the sdo/sa0 pin is connected to the voltage supply, the address is 0011101b, otherwise, if the sdo/sa0 pin is connected to ground, the address is 0011110b. this solution permits the connection and addressing of two different accelerometers to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded in the LSM303D behaves as a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-address is transmitted: the 7 lsb represent the actual register address while the msb enables address auto-increment. if the msb of the sub field is 1, the sub (register address) is automatically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master transmits to the slave with direction unchanged. table 11 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 11. sad+read/write patterns command sdo/sa0 pin sad[6:2] sad[1:0] r/w sad+r/w read 0 00111 10 1 3d write 0 00111 10 0 3c read 1 00111 01 1 3b write 1 00111 01 0 3a table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
docid023312 rev 2 23/52 LSM303D digital interfaces 52 data is transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes sent per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line, scl, low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to ?1? while sub(6-0) represents the address of the first register to be read. in the communication format presented, mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the spi is a bus slave. the spi allows writing and reading the registers of the device. the serial interface interacts with the outside world through 4 wires: cs , spc , sdi and sdo . table 13. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 14. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
digital interfaces LSM303D 24/52 docid023312 rev 2 figure 6. read and write protocol cs is the serial port enable and is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. these lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/write bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : r w bit. when 0, the data di(7:0) is written to the device. when 1, the data do(7:0) from the device is read. in the latter case the chip drives sdo at the start of bit 8. bit 1 : m s bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto-incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written to the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands, further blocks of 8 clock periods are added. when the m s bit is 0, the address used to read/write data remains the same for every block. when the m s bit is 1, the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7do6do5do4do3do2do1do0 ms am10129v1
docid023312 rev 2 25/52 LSM303D digital interfaces 52 6.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. the multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads. figure 8. multiple byte spi read protocol (2-byte example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms am10130v1 cs sp c sdi sd o rw do7do6do5do4do3do2 do1do0 ad5 ad4 ad 3 ad2 ad1 ad0 do 15 do 14 do 13 do 12 do 11 do 10 d o9 d o8 ms am10131v1
digital interfaces LSM303D 26/52 docid023312 rev 2 6.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 clock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1 : m s bit. when 0, do not increment address; when 1, increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written to the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 10. multiple byte spi write protocol (2-byte example) 6.2.3 spi read in 3-wire mode 3-wire mode is entered by setting the bit sim (spi serial interface mode selection) to ?1? in ctrl2 (21h) . cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad 4 ad 3 ad2 ad 1 ad0 ms am10132v1 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 13 d i1 2 di 11 di 10 di 9 di 8 ms am10133v1
docid023312 rev 2 27/52 LSM303D digital interfaces 52 figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : m s bit. when 0, does not increment the address; when 1, increments the address in multiple reads. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad 4 ad 3 ad2 ad1 ad 0 ms am10134v1
output register mapping LSM303D 28/52 docid023312 rev 2 7 output register mapping the table below provides a listing of the 8-bit registers embedded in the device and the corresponding addresses. table 16. register address map name type register address default comment hex binary reserved -- 00-04 -- -- reserved temp_out_l r 05 000 0101 output temp_out_h r 06 000 0110 output status_m r 07 000 0111 output out_x_l_m r 08 000 1000 output out_x_h_m r 09 000 1001 output out_y_l_m r 0a 000 1010 output out_y_h_m r 0b 000 1011 output out_z_l_m r 0c 000 1100 output out_z_h_m r 0d 000 1101 output reserved -- 0e 000 1110 -- reserved who_am_i r 0f 000 1111 01001001 reserved -- 10-11 -- -- reserved int_ctrl_m rw 12 001 0010 11101000 int_src_m r 13 001 0011 output int_ths_l_m rw 14 001 0100 00000000 int_ths_h_m rw 15 001 0101 00000000 offset_x_l_m rw 16 001 0110 00000000 offset_x_h_m rw 17 001 0111 00000000 offset_y_l_m rw 18 001 01000 00000000 offset_y_h_m rw 19 001 01001 00000000 offset_z_l_m rw 1a 001 01010 00000000 offset_z_h_m rw 1b 001 01011 00000000 reference_x rw 1c 001 01100 00000000 reference_y rw 1d 001 01101 00000000 reference_z rw 1e 001 01110 00000000 ctrl0 rw 1f 001 1111 00000000 ctrl1 rw 20 010 0000 00000111 ctrl2 rw 21 010 0001 00000000
docid023312 rev 2 29/52 LSM303D output register mapping 52 registers marked as reserved must not be changed. writing to these registers may cause permanent damage to the device.the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. ctrl3 rw 22 010 0010 00000000 ctrl4 rw 23 010 0011 00000000 ctrl5 rw 24 010 0100 00011000 ctrl6 rw 25 010 0101 00100000 ctrl7 rw 26 010 0110 00000001 status_a r 27 010 0111 output out_x_l_a r 28 010 1000 output out_x_h_a r 29 010 1001 output out_y_l_a r 2a 010 1010 output out_y_h_a r 2b 010 1011 output out_z_l_a r 2c 010 1100 output out_z_h_a r 2d 010 1101 output fifo_ctrl rw 2e 010 1110 00000000 fifo_src r 2f 010 1111 output ig_cfg1 rw 30 011 0000 00000000 ig_src1 r 31 011 0001 output ig_ths1 rw 32 011 0010 00000000 ig_dur1 rw 33 011 0011 00000000 ig_cfg2 rw 34 011 0100 00000000 ig_src2 r 35 011 0101 output ig_ths2 rw 36 011 0110 00000000 ig_dur2 rw 37 011 0111 00000000 click_cfg rw 38 011 1000 00000000 click_src r 39 011 1001 output click_ths rw 3a 011 1010 00000000 time_limit rw 3b 011 1011 00000000 time _latency rw 3c 011 1100 00000000 time_window rw 3d 011 1101 00000000 act_ths rw 3e 011 1110 00000000 act_dur rw 3f 011 1111 00000000 table 16. register address map (continued) name type register address default comment hex binary
register description LSM303D 30/52 docid023312 rev 2 8 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration and magnetic data. the register address, consisting of 7 bits, is used to identify them and to write the data through the serial interface. 8.1 temp_out_l (05h), temp_out_h (06h) temperature sensor data. temperature data is stored as two?s complement data in 12-bit format, right-justified. refer to section 4.2 for details on how to enable and read the temperature sensor output data. 8.2 status_m (07h) table 17. status_m register zyxmor/ tempor zmor ymor xmor zyxmda / tempda zmda ymda xmda table 18. status_m register description zyxmor/ tempor magnetic x, y and z-axis and temperature data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous data) temperature data overrun if t_only bit in ctrl7 (26h) is set to ?1?. default value: 0. zmor z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) ymor y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xmor x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxmda/ tempda x, y and z-axis and temperature new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) temperature new data available if the t_only bit in ctrl7 (26h) is set to ?1?. zmda z-axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) ymda y-axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xmda x-axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available)
docid023312 rev 2 31/52 LSM303D register description 52 8.3 out_x_l_m (08h), out_x_h_m (09h) x-axis magnetic data. the value is expressed in 16-bit as two?s complement. 8.4 out_y_l_m (0ah), out_y_h_m (0bh) y-axis magnetic data. the value is expressed in 16-bit as two?s complement. 8.5 out_z_l_m (0ch), out_z_h_m (0dh) z-axis magnetic data. the value is expressed in 16-bit as two?s complement. 8.6 who_am_i (0fh) device identification register. 8.7 int_ctrl_m (12h) table 19. who_am_i register 010 01001 table 20. int_ctrl_m register xmien ymien zmien pp_od iea miel 4d mien table 21. int_ctrl_m register description xmien enable interrupt recognition on x-axis for magnetic data. default value: 0. (0: disable interrupt recognition; 1: enable interrupt recognition) ymien enable interrupt recognition on y-axis for magnetic data. default value: 0. (0: disable interrupt recognition; 1: enable interrupt recognition) zmien enable interrupt recognition on z-axis for magnetic data. default value: 0. (0: disable interrupt recognition; 1: enable interrupt recognition) pp_od interrupt pin configuration. default value: 0. (0: push-pull; 1: open drain) iea interrupt polarity. default value: 0. (0: interrupt active-low; 1: interrupt active-high) miel latch interrupt request on int_src_m (13h) register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) once the miel is set to ?1?, the interrupt is cleared by reading the int_src_m (13h) register. 4d 4d enable: 4d detection on acceleration data is enabled when 6d bit in ig_cfg1 (30h) is set to 1. default value: 0. mien enable interrupt generation for magnetic data. default value: 0. (0: disable interrupt generation; 1: enable interrupt generation)
register description LSM303D 32/52 docid023312 rev 2 8.8 int_src_m (13h) 8.9 int_ths_l_m (14h), int_ths_h_m (15h) magnetic interrupt threshold. default value: 0. the value is expressed in 16-bit unsigned. even if the threshold is expressed in absolute value, the device detects both positive and negative thresholds. table 22. int_src_m register m_pth_x m_pth_y m_pth_z m_nth_x m_nth_y m_nth_z mroi mint table 23. int_src_m register description m_pth_x magnetic value on x-axis exceeds the threshold on the positive side. default value: 0. m_pth_y magnetic value on y-axis exceeds the threshold on the positive side. default value: 0. m_pth_z magnetic value on z-axis exceeds the threshold on the positive side. default value: 0. m_nth_x magnetic value on x-axis exceeds the threshold on the negative side. default value: 0. m_nth_y magnetic value on y-axis exceeds the threshold on the negative side. default value: 0. m_nth_z magnetic value on z-axis exceeds the threshold on the negative side. default value: 0. mroi internal measurement range overflow on magnetic value. default value: 0. mint magnetic interrupt event. the magnetic field value exceeds the threshold. default value: 0. table 24. int_ths_l_m register ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 25. int_ths_h_m register 0 ths14 ths13 ths12 ths11 ths10 ths9 ths8
docid023312 rev 2 33/52 LSM303D register description 52 8.10 offset_x_l_m (16h), offset_x_h_m (17h) magnetic offset for x-axis. default value: 0. the value is expressed in 16-bit as two?s complement. 8.11 offset_y_l_m (18h), offset_y_h_m (19h) magnetic offset for y-axis. default value: 0. the value is expressed in 16-bit as two?s complement. 8.12 offset_z_l_m (1ah), offset_z_h_m (1bh) magnetic offset for z-axis. default value: 0. the value is expressed in 16-bit as two?s complement. 8.13 reference_x (1ch) reference value for high-pass filter for x-axis acceleration data. 8.14 reference_y (1dh) reference value for high-pass filter for y-axis acceleration data. table 26. offset_x_l_m register off_x_7 off_x_6 off_x_5 off_x_4 off_x_3 off_x_2 off_x_1 off_x_0 table 27. offset_x_h_m register off_x_15 off_x_14 off_x_13 off_x_12 off_x_11 off_x_10 off_x_9 off_x_8 table 28. offset_y_l_m register off_y_7 off_y_6 off_y_5 off_y_4 off_y_3 off_y_2 off_y_1 off_y_0 table 29. offset_y_h_m register off_y_15 off_y_14 off_y_13 off_y_12 off_y_11 off_y_10 off_y_9 off_y_8 table 30. offset_z_l_m register off_z_7 off_z_6 off_z_5 off_z_4 off_z_3 off_z_2 off_z_1 off_z_0 table 31. offset_z_h_m register off_z_15 off_z_14 off_z_13 off_z_12 off_z_11 off_z_10 off_z_9 off_z_8
register description LSM303D 34/52 docid023312 rev 2 8.15 reference_z (1eh) reference value for high-pass filter for z-axis acceleration data. 8.16 ctrl0 (1fh) 8.17 ctrl1 (20h) table 32. ctrl0 register boot fifo_en fth_en 0 (1) 1. these bits must be set to ?0? for correct operation of the device. 0 (1) hp_click hpis1 hpis2 table 33. ctrl0 register description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) fifo_en fifo enable. default value: 0 (0: fifo disable; 1: fifo enable) fth_en fifo programmable threshold enable. default value: 0 (0: disable; 1: enable) hp_click high-pass filter enabled for click function. default value: 0 (0: filter bypassed; 1: filter enabled) hpis1 high-pass filter enabled for interrupt generator 1. default value: 0 (0: filter bypassed; 1: filter enabled) hpis2 high-pass filter enabled for interrupt generator 2. default value: 0 (0: filter bypassed; 1: filter enabled) table 34. ctrl1 register aodr3 aodr2 aodr1 aodr0 bdu azen ayen axen table 35. ctrl1 register description aodr [3:0] acceleration data - rate selection. default value: 0000 (0000: power-down mode; others: refer to table 36 ) bdu block data update for acceleration and magnetic data. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb have been read) azen acceleration z-axis enable. default value: 1 (0: z-axis disabled; 1: z-axis enabled) ayen acceleration y-axis enable. default value: 1 (0: y-axis disabled; 1: y-axis enabled) axen acceleration x-axis enable. default value: 1 (0: x-axis disabled; 1: x-axis enabled)
docid023312 rev 2 35/52 LSM303D register description 52 aodr [3:0] is used to set power mode and odr selection. in the following table bit selection of aodr [3:0] for all frequencies is shown. 8.18 ctrl2 (21h) table 36. acceleration data rate configuration aodr3 aodr2 aodr1 aodr0 power mode and odr selection 0 0 0 0 power-down mode 0 0 0 1 3.125 hz 0 0 1 0 6.25 hz 0 0 1 1 12.5 hz 0 1 0 0 25 hz 0 1 0 1 50 hz 0 1 1 0 100 hz 0 1 1 1 200 hz 1 0 0 0 400 hz 1 0 0 1 800 hz 1 0 1 0 1600 hz table 37. ctrl2 register abw1 abw0 afs2 afs1 afs0 0 (1) 1. this bit must be set to ?0? for correct operation of the device. ast sim table 38. ctrl2 register description abw[1:0] accelerometer anti-alias filter bandwidth. default value: 00 refer to table 39 afs[2:0] acceleration full-scale selection. default value: 000 refer to table 40 ast acceleration self-test enable. default value: 0 (0: self-test disabled; 1: self-test enabled) sim spi serial interface mode selection. default value: 0 (0: 4-wire interface; 1: 3-wire interface) table 39. acceleration anti-alias filter bandwidth abw1 abw0 anti-alias filter bandwidth 0 0 773 hz 0 1 194 hz
register description LSM303D 36/52 docid023312 rev 2 8.19 ctrl3 (22h) 1 0 362 hz 1 1 50 hz table 40. acceleration full-scale selection afs2 afs1 afs0 acceleration full scale 0 0 0 2 g 0 0 1 4 g 0 1 0 6 g 0 1 1 8 g 1 0 0 16 g table 39. acceleration anti-alias filter bandwidth abw1 abw0 anti-alias filter bandwidth table 41. ctrl3 register int1 _boot int1 _click int1 _ig1 int1 _ig2 int1 _igm int1 _drdy_a int1 _drdy_m int1 _empty table 42. ctrl3 register description int1_boot boot on int1 enable. default value: 0 (0: disable; 1: enable) int1_click click generator interrupt on int1. default value: 0 (0: disable; 1: enable) int1_ig1 inertial interrupt generator 1 on int1. default value: 0 (0: disable; 1: enable) int1_ig2 inertial interrupt generator 2 on int1. default value: 0 (0: disable; 1: enable) int1_igm magnetic interrupt generator on int1. default value: 0 (0: disable; 1: enable) int1_drdy_a accelerometer data-ready signal on int1. default value: 0 (0: disable; 1: enable) int1_drdy_m magnetometer data-ready signal on int1. default value: 0 (0: disable; 1: enable) int1_empty fifo empty indication on int1. default value: 0 (0: disable; 1: enable)
docid023312 rev 2 37/52 LSM303D register description 52 8.20 ctrl4 (23h) 8.21 ctrl5 (24h) table 43. ctrl4 register int2 _click int2 _int1 int2 _int2 int2 _intm int2 _drdy_a int2 _drdy_m int2 _overrun int2 _fth table 44. ctrl4 register description int2 _click click generator interrupt on int2. default value: 0 (0: disable; 1: enable) int2 _ig1 inertial interrupt generator 1 on int2. default value: 0 (0: disable; 1: enable) int2 _ig2 inertial interrupt generator 2 on int2. default value: 0 (0: disable; 1: enable) int2 _igm magnetic interrupt generator on int2. default value: 0 (0: disable; 1: enable) int2 _drdy_a accelerometer data-ready signal on int2. default value: 0 (0: disable; 1: enable) int2 _drdy_m magnetometer data-ready signal on int2. default value: 0 (0: disable; 1: enable) int2 _overrun fifo overrun interrupt on int2. default value: 0 (0: disable; 1: enable) int2 _fth fifo threshold interrupt on int2. default value: 0 (0: disable; 1: enable) table 45. ctrl5 register temp_en m_res1 m_res0 m_odr2 m_odr1 m_odr0 lir2 lir1 table 46. ctrl5 register description temp_en temperature sensor enable. default value: 0 (0: temperature sensor disabled; 1: temperature sensor enabled) m_res [1:0] magnetic resolution selection. default value: 00 (00: low resolution, 11: high resolution) m_odr [2:0] magnetic data rate selection. default value: 110 refer to table 47 lir2 latch interrupt request on int2_src register, with int2_src register cleared by reading int2_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) lir1 latch interrupt request on int1_src register, with int1_src register cleared by reading int1_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched)
register description LSM303D 38/52 docid023312 rev 2 8.22 ctrl6 (25h) 8.23 ctrl7 (26h) table 47. magnetic data rate configuration modr2 modr1 modr0 odr selection 0 0 0 3.125 hz 0 0 1 6.25 hz 0 1 0 12.5 hz 0 1 1 25 hz 1 0 0 50 hz 1 0 1 100 hz (1) 1. available only for accelerometer odr > 50 hz or accelerometer in power-down mode (refer to table 36, aodr setting). 1 1 0 do not use 1 1 1 reserved table 48. ctrl6 register 0 (1) mfs1 mfs0 0 (1) 1. these bits must be set to ?0? for correct operation of the device. 0 (1) 0 (1) 0 (1) 0 (1) table 49. ctrl6 register description mfs [1:0] magnetic full-scale selection. default value: 01 refer to table 50 table 50. magnetic full-scale selection mfs1 mfs0 magnetic full scale 0 0 2 gauss 0 1 4 gauss 1 0 8 gauss 1 1 12 gauss table 51. ctrl7 register ahpm1 ahpm0 afds t_only 0 (1) 1. this bit must be set to ?0? for correct operation of the device. mlp md1 md0
docid023312 rev 2 39/52 LSM303D register description 52 8.24 status_a (27h) table 52. ctrl7 register description ahpm[1:0] high-pass filter mode selection for acceleration data. default value: 00 refer to table 53 afds filtered acceleration data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and fifo) t_only temperature sensor only mode. default value: 0 if this bit is set to ?1?, the temperature sensor is on while the magnetic sensor is off. mlp magnetic data low-power mode. default value: 0 if this bit is ?1?, the m_odr [2:0] is set to 3.125 hz independently from the modr set- tings. once the bit is set to ?0?, the magnetic data rate is configured by the modr bits in the ctrl5 (24h) register. md[1:0] magnetic sensor mode selection. default 10 refer to table 54 table 53. high-pass filter mode selection ahpm1 ahpm0 high-pass filter mode 0 0 normal mode (reset x, y and z-axis, reading respective reference_x (1ch) , reference_y (1dh) and reference_z (1eh) registers) 0 1 reference signal for filtering 1 0 normal mode 1 1 auto-reset on interrupt event table 54. magnetic sensor mode selection md1 md0 magnetic sensor mode 0 0 continuous-conversion mode 0 1 single-conversion mode 1 0 power-down mode 1 1 power-down mode table 55. status_a register zyxaor zaor yaor xaor zyxada zada yada xada
register description LSM303D 40/52 docid023312 rev 2 8.25 out_x_l_a (28h), out_x_h_a (29h) x-axis acceleration data. the value is expressed in 16-bit as two?s complement. 8.26 out_y_l_a (2ah), out_y_h_a (2bh) y-axis acceleration data. the value is expressed in 16-bit as two?s complement. 8.27 out_z_l_a (2ch), out_z_h_a (2dh) z-axis acceleration data. the value is expressed in 16-bit as two?s complement. 8.28 fifo_ctrl (2eh) table 56. status_a register description zyxaor acceleration x, y and z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous data) zaor acceleration z-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis has overwritten the previous data) yaor acceleration y-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous data) xaor acceleration x-axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous data) zyxada acceleration x, y and z-axis new value available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zada acceleration z-axis new value available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yada acceleration y-axis new value available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xada acceleration x-axis new value available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available) table 57. fifo_ctrl register fm2 fm1 fm0 fth4 fth3 fth2 fth1 fth0 table 58. fifo_ctrl register description fm[2:0] fifo mode selection. default value: 000 refer to table 59 fth[4:0] fifo threshold level. default value: 00000
docid023312 rev 2 41/52 LSM303D register description 52 interrupt generator 2 can change the fifo mode. 8.29 fifo_src (2fh) fifo status register. 8.30 ig_cfg1 (30h) inertial interrupt generator 1 configuration register. table 59. fifo mode configuration fm2 fm1 fm0 fifo mode 0 0 0 bypass mode 0 0 1 fifo mode 0 1 0 stream mode 0 1 1 stream-to-fifo mode 1 0 0 bypass-to-stream mode table 60. fifo_src register fth ovrn empty fss4 fss3 fss2 fss1 fss0 table 61. fifo_src register description fth fifo threshold status. fth bit is set to ?1? when fifo content exceeds threshold level. ovrn fifo overrun status. ovrn bit is set to ?1? when fifo buffer is full. empty empty status. empty bit is set to ?1? when all fifo samples have been read and fifo is empty. fss[4:0] fifo stored data level. fss4-0 bits contain the current number of unread fifo levels. table 62. ig_cfg1 register aoi 6d zhie/ zupe zlie/ zdowne yhie/ yupe ylie/ ydowne xhie/ xupe xlie/ xdowne
register description LSM303D 42/52 docid023312 rev 2 content of this register is loaded at boot. write operation at this address is possible only after system boot. difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when orientation moves from an unknown zone to a known zone. the interrupt signal stays for a duration odr. aoi-6d = ?11? is direction recognition. an interrupt is generated when orientation is inside a known zone. the interrupt signal stays until orientation is inside the zone. 8.31 ig_src1 (31h) inertial interrupt generator 1 status register. table 63. ig_cfg1 register description aoi and/or combination of interrupt events. default value: 0. refer to table 64 6d 6-direction detection function enabled. default value: 0. refer to table 64 zhie/ zupe enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie/ zdowne enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie/ yupe enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) ylie/ ydowne enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xhie/ xupe enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xlie/ xdowne enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) table 64. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition table 65. ig_src1 register 0 ia zhzlyhylxhxl
docid023312 rev 2 43/52 LSM303D register description 52 reading at this address clears the ig_src1 (31h) ia bit (and the interrupt signal on the corresponding interrupt pin) and allows the refreshment of data in the ig_src1 (31h) register if the latched option was chosen. 8.32 ig_ths1 (32h) 8.33 ig_dur1 (33h) the d6 - d0 bits set the minimum duration of the interrupt 1 event to be recognized. duration steps and maximum values depend on the odr chosen. table 66. ig_src1 register description ia interrupt status. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt; 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt; 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt; 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt; 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt; 1: x low event has occurred) table 67. ig_ths1 register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 68. ig_ths1 register description ths[6:0] interrupt generator 1 threshold. default value: 000 0000 table 69. ig1_dur1 register 0 d6d5d4d3d2d1d0 table 70. ig1_dur1 register description d[6:0] duration value. default value: 000 0000
register description LSM303D 44/52 docid023312 rev 2 8.34 ig_cfg2 (34h) this register contains the settings for the inertial interrupt generator 2. content of this register is loaded at boot. write operation at this address is possible only after system boot. difference between aoi-6d = ?01? and aoi-6d = ?11?. aoi-6d = ?01? is movement recognition. an interrupt is generated when the orientation moves from an unknown zone to a known zone. the interrupt signal remains for a duration odr. aoi-6d = ?11? is direction recognition. an interrupt is generated when the orientation is inside a known zone. the interrupt signal remains until the orientation is inside the zone. table 71. ig_cfg2 register aoi 6d zhie/ zupe zlie/ zdowne yhie/ yupe ylie/ ydowne xhie/ xupe xlie/ xdowne table 72. ig_cfg2 register description aoi and/or combination of interrupt events. default value: 0. refer to table 73 6d 6-direction detection function enabled. default value: 0. refer to table 73 zhie/ zupe enable interrupt generation on z high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) zlie/ zdowne enable interrupt generation on z low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request) yhie/ yupe enable interrupt generation on y high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) ylie/ ydowne enable interrupt generation on y low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xhie/ xupe enable interrupt generation on x high event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) xlie/ xdowne enable interrupt generation on x low event or on direction recognition. default value: 0 (0: disable interrupt request; 1: enable interrupt request.) table 73. interrupt mode aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6-direction movement recognition 1 0 and combination of interrupt events 1 1 6-direction position recognition
docid023312 rev 2 45/52 LSM303D register description 52 8.35 ig_src2 (35h) this register contains the status for the inertial interrupt generator 2. reading at this address clears the ig_src2 (35h) ia bit (and the interrupt signal on the corresponding interrupt pin) and allows the refresh of data in the ig_src2 (35h) register if the latched option was chosen. 8.36 ig_ths2 (36h) 8.37 ig_dur2 (37h) table 74. ig_src2 register 0 ia zhzlyhylxhxl table 75. ig_src2 register description ia interrupt generator 2 status. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt; 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt; 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt; 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt; 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt; 1: x low event has occurred) table 76. ig2_ths2 register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 77. ig2_ths2 register description ths[6:0] interrupt generator 2 threshold. default value: 000 0000 table 78. ig_dur2 register 0 d6d5d4d3d2d1d0
register description LSM303D 46/52 docid023312 rev 2 the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration steps and maximum values depend on the odr chosen. 8.38 click_cfg (38h) table 79. ig_dur2 register description d6 - d0 duration value. default value: 000 0000 table 80. click_cfg register -- -- zd zs yd ys xd xs table 81. click_cfg register description zd enable interrupt double-click on z-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zs enable interrupt single-click on z-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) yd enable interrupt double-click on y-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ys enable interrupt single-click on y-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xd enable interrupt double-click on x-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xs enable interrupt single-click on x-axis. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)
docid023312 rev 2 47/52 LSM303D register description 52 8.39 click_src (39h) 8.40 click_ths (3ah) 8.41 time_limit (3bh) table 82. click_src register -- ia dclick sclick sign z y x table 83. click_src register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) dclick double-click enable. default value: 0 (0: double-click detection disable; 1: double-click detection enable) sclick single-click enable. default value: 0 (0: single-click detection disable; 1: single-click detection enable) sign click sign. 0: positive detection; 1: negative detection z z-click detection. default value: 0 (0: no interrupt; 1: z high event has occurred) y y-click detection. default value: 0 (0: no interrupt; 1: y high event has occurred) x x-click detection. default value: 0 (0: no interrupt; 1: x high event has occurred) table 84. click_ths register - ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 85. click_ths register description ths[6:0] click threshold. default value: 000 0000 table 86. time_limit register - tli6 tli5 tli4 tli3 tli2 tli1 tli0 table 87. time_limit register description tli[6:0] click time limit. default value: 000 0000
register description LSM303D 48/52 docid023312 rev 2 8.42 time_latency (3ch) 8.43 time_window (3dh) 8.44 act_ths (3eh) 8.45 act_dur (3fh) table 88. time_latency register tla7 tla6 tla5 tla4 tla3 tla2 tla1 tla0 table 89. time_latency register description tla[7:0] double-click time latency. default value: 0000 0000 table 90. time_window register tw7 tw6 tw5 tw4 tw3 tw2 tw1 tw0 table 91. time_window register description tw[7:0] double-click time window table 92. act_ths register -- acth6 acth5 acth4 acth3 acth2 acth1 acth0 table 93. act_ths register description acth[6:0] sleep-to-wake, return-to-sleep activation threshold 1 lsb = 16 m g table 94. act_dur register actd7 actd6 actd5 actd4 actd3 actd2 actd1 actd0 table 95. act_dur register description actd[7:0] sleep-to-wake, return-to-sleep duration dur = (act_dur + 1)*8/odr
docid023312 rev 2 49/52 LSM303D package information 52 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
package information LSM303D 50/52 docid023312 rev 2 figure 12. lga 3x3x1.0 16l mechanical drawing table 96. lga 3x3x1.0 16l mechanical data dim. mm min. typ. max. a1 1 a2 0.785 a3 0.200 d1 2.850 3.000 3.150 e1 2.850 3.000 3.150 l1 1.000 1.060 l2 2.000 2.060 n1 0.500 n2 1.000 m 0.040 0.100 p1 0.875 p2 1.275 t1 0.290 0.350 0.410 t2 0.190 0.250 0.310 d 0.150 k 0.050 7983231_m
docid023312 rev 2 51/52 LSM303D revision history 52 10 revision history table 97. document revision history date revision changes 22-jun-2012 1 initial release 05-nov-2013 2 document status promoted from preliminary to production data changed abbreviation of magnetic sensitivity to m_so and updated footnote 6 in table 3: sensor characteristics added esd to table 8: absolute maximum ratings minor textual updates throughout document
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